September 2022 Archives by thread
Starting: Thu Sep 1 09:25:31 BST 2022
Ending: Fri Sep 30 21:21:18 BST 2022
Messages: 408
- [Libre-soc-bugs] [Bug 917] New: pysvp64dis: support SVP64 disassembly
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 899] implement additional Transcendentals in simulator
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 918] New: pysvp64dis: introduce single source of truth for instructions (instruction database)
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 919] New: pysvp64dis: disassemble word instructions
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 920] New: pysvp64dis: disassemble SVP64 instructions
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 921] New: pysvp64dis: support instruction aliases
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 838] sync or at least statically check fields.text, power_decoder, trans/svp64, CSVs between each other
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 845] binutils: drop svmagic and deal with the prefix instead
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 889] eth_mac VLSI Layout in tsmc180 and sky130
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 197] Formal correctness proof needed of the 6600-style Out-of-Order execution engine
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 797] Add 10/100 OpenCores Ethernet MAC
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 231] Video Opcodes Standards writeup
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 507] ls180 asic needs an ioring, pads need defining and connecting
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 203] potential improvements to coriolis2 for LibreSOC Layout
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 200] IEEE754 FPU Coriolis2 layout
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 521] small example using JTAG for testing coriolis2 new multi clock plugin
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 236] Atomics Standard writeup needed
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 728] ISACaller needs a cleanup and partial re-factoring
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 421] TRAP pipeline formal correctness proof needed
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 565] Improve formal verification on PartitionedSignal
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 578] python-based svp64 "generator" class
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 857] binutils: provide tests for setvl/svstep/svshape/svremap
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 887] implement fmvis and 2nd-half variant
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 232] Implementation of video opcodes in simulator
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 52] software simulator compliant with the latest SimpleV Vectorisation Standard (SVP64)
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 137] NLNet 2019 Video Acceleration Proposal 2019-10-031
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 233] Audio and Video unit tests needed to be run in simulator
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 234] Hardware implementation of video opcodes
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 884] sync pysvp64asm register parsing
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 758] pypowersim and how to run bare metal programs/functions is needed
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 911] svshape2 instruction (with offsets)
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 254] Second iteration round for opcodes, simulation and hardware for 3D MESA
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 879] Formal proof of soc.experiment.compalu_multi.MultiCompUnit needed
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 418] SPR pipeline formal correctness proof needed
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 835] add support for smtlib2 floating-point to yosys and nmigen
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 867] add svindex instruction to binutils (and openpower-isa infrastructure)
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 864] implement parallel prefix reduction in simulator
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 7] SD/MMC and eMMC interface needed
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 127] Transcendentals needed (SIN/COS/ATAN2/EXP/LOG/POW etc.)
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 863] AV opcode implementation, add to Decoder, CSV files
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 588] add SVP64 to PowerDecoder2
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 925] New: SVP64 example bcd
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 927] New: sv.setvl with RT>=32 fails at the moment
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 890] Static Timing Analysis of eth_mac
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 340] formal proof of POWER9 SHIFTROT pipeline needed
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 419] MUL pipeline formal proof needed
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 844] binutils: implement the first revision with magic instruction
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 849] binutils: parse macros in SVP64 and refactor code
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 834] binutils: support draft fsins/fcoss/ternlogi instructions
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 898] binutils svp64 objdump support
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 252] 3D accelerated opcodes need to be added to the POWER ISA simulator
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 705] add ISACaller simulator FPSCR support
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 228] VP9 optimizations
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 846] Pinmux Pinspec Interconnect Auto-Generation
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 872] binutil needs support for new Pack/Unpack modes
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 550] binutils support needed for svp64
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 222] JPEG optimizations
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 659] SVP64 demo / unit test of CRM data-dependent ffirst mode implementing insertion sort
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 929] New: maddld and friends incorrectly ignored by sv_analysis.py
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 931] New: binutils: segaults building SVP64 asm
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 932] New: [simulator]
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 934] New: Evaluation of optimized placement for Yosys generated SRAM
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 935] New: ISACaller doesn't handle instructions that write to both RT and RS
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 223] MPEG1/2 optimizations
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 158] NLNet 2019 Formal Correctness Proofs toplevel 2019-10-032
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 836] binutils: support the rest of bitmanip instructions
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 227] VP8 optimizations
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 138] NLNet 2019 Coriolis2 Layout proposal 2019-10-029
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 855] add libre-soc to kestrel
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 850] NGI POINTER Milestone 3
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 861] PowerEL ppc64sffs building hardware
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 870] FPGA equipment for NGI POINTER (2)
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 790] dev-env-setup script for nextpnr-xilinx
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 229] AV1 optimizations
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 745] OP_TERNLOG instruction
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 174] NLNet 2019 Formal Standards OpenPOWER proposal 2019-10-046
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 239] FP16 (and FP128) POWER Formal Standard proposal
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 243] Documentation budget for OpenPower Member discussion and proposals
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 242] OpenPOWER simulation unit tests are needed
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 710] Convert decoder tests over to use alu case and expected state format
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 738] ISACaller modifies initial_sprs of test data
bugzilla-daemon at libre-soc.org
- [Libre-soc-bugs] [Bug 717] Document Power ISA test API
bugzilla-daemon at libre-soc.org
Last message date:
Fri Sep 30 21:21:18 BST 2022
Archived on: Fri Sep 30 21:21:22 BST 2022
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