[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #39 from Dmitry Selyutin <ghostmansd at gmail.com> ---
Refactored RM modes, since we're approaching to the stage where some modes
reuse existing fields for their needs (e.g. cr_ops reuse ewsrc). Setting these
in ewsrc is not obvious; however, when you do `insn.prefix.rm.cr_ops.sz = 1`,
it is way clearer. Below is what we have now. Note that some fields are present
in base RM class: I didn't want to duplicate all these fields in all children
subclasses. This leads to the fact that say insn.prefix.rm.cr_ops will also
have ewsrc inherited, it just won't be used.

RM.mmode
RM.mask
RM.elwidth
RM.ewsrc
RM.subvl
RM.mode
RM.smask
RM.extra
RM.extra2
RM.extra2.idx0
RM.extra2.idx1
RM.extra2.idx2
RM.extra2.idx3
RM.extra3
RM.extra3.idx0
RM.extra3.idx1
RM.extra3.idx2
RM.normal
RM.normal.mmode
RM.normal.mask
RM.normal.elwidth
RM.normal.ewsrc
RM.normal.subvl
RM.normal.mode
RM.normal.smask
RM.normal.extra
RM.normal.extra2
RM.normal.extra2.idx0
RM.normal.extra2.idx1
RM.normal.extra2.idx2
RM.normal.extra2.idx3
RM.normal.extra3
RM.normal.extra3.idx0
RM.normal.extra3.idx1
RM.normal.extra3.idx2
RM.normal.simple
RM.normal.simple.dz
RM.normal.simple.sz
RM.normal.smr
RM.normal.smr.RG
RM.normal.pmr
RM.normal.svmr
RM.normal.svmr.SVM
RM.normal.pu
RM.normal.pu.SVM
RM.normal.ffrc1
RM.normal.ffrc1.inv
RM.normal.ffrc1.CR
RM.normal.ffrc0
RM.normal.ffrc0.inv
RM.normal.ffrc0.VLi
RM.normal.ffrc0.RC1
RM.normal.sat
RM.normal.sat.N
RM.normal.sat.dz
RM.normal.sat.sz
RM.normal.satx
RM.normal.satx.N
RM.normal.satx.zz
RM.normal.satx.dz
RM.normal.satx.sz
RM.normal.satpu
RM.normal.satpu.N
RM.normal.satpu.zz
RM.normal.satpu.dz
RM.normal.satpu.sz
RM.normal.prrc1
RM.normal.prrc1.inv
RM.normal.prrc1.CR
RM.normal.prrc0
RM.normal.prrc0.inv
RM.normal.prrc0.zz
RM.normal.prrc0.RC1
RM.normal.prrc0.dz
RM.normal.prrc0.sz
RM.ldst_imm
RM.ldst_imm.mmode
RM.ldst_imm.mask
RM.ldst_imm.elwidth
RM.ldst_imm.ewsrc
RM.ldst_imm.subvl
RM.ldst_imm.mode
RM.ldst_imm.smask
RM.ldst_imm.extra
RM.ldst_imm.extra2
RM.ldst_imm.extra2.idx0
RM.ldst_imm.extra2.idx1
RM.ldst_imm.extra2.idx2
RM.ldst_imm.extra2.idx3
RM.ldst_imm.extra3
RM.ldst_imm.extra3.idx0
RM.ldst_imm.extra3.idx1
RM.ldst_imm.extra3.idx2
RM.ldst_imm.simple
RM.ldst_imm.simple.zz
RM.ldst_imm.simple.els
RM.ldst_imm.simple.dz
RM.ldst_imm.simple.sz
RM.ldst_imm.spu
RM.ldst_imm.spu.zz
RM.ldst_imm.spu.els
RM.ldst_imm.spu.dz
RM.ldst_imm.spu.sz
RM.ldst_imm.ffrc1
RM.ldst_imm.ffrc1.inv
RM.ldst_imm.ffrc1.CR
RM.ldst_imm.ffrc0
RM.ldst_imm.ffrc0.inv
RM.ldst_imm.ffrc0.els
RM.ldst_imm.ffrc0.RC1
RM.ldst_imm.sat
RM.ldst_imm.sat.N
RM.ldst_imm.sat.zz
RM.ldst_imm.sat.els
RM.ldst_imm.sat.dz
RM.ldst_imm.sat.sz
RM.ldst_imm.prrc1
RM.ldst_imm.prrc1.inv
RM.ldst_imm.prrc1.CR
RM.ldst_imm.prrc0
RM.ldst_imm.prrc0.inv
RM.ldst_imm.prrc0.els
RM.ldst_imm.prrc0.RC1
RM.ldst_idx
RM.ldst_idx.mmode
RM.ldst_idx.mask
RM.ldst_idx.elwidth
RM.ldst_idx.ewsrc
RM.ldst_idx.subvl
RM.ldst_idx.mode
RM.ldst_idx.smask
RM.ldst_idx.extra
RM.ldst_idx.extra2
RM.ldst_idx.extra2.idx0
RM.ldst_idx.extra2.idx1
RM.ldst_idx.extra2.idx2
RM.ldst_idx.extra2.idx3
RM.ldst_idx.extra3
RM.ldst_idx.extra3.idx0
RM.ldst_idx.extra3.idx1
RM.ldst_idx.extra3.idx2
RM.ldst_idx.simple
RM.ldst_idx.simple.SEA
RM.ldst_idx.simple.sz
RM.ldst_idx.simple.dz
RM.ldst_idx.stride
RM.ldst_idx.stride.SEA
RM.ldst_idx.stride.dz
RM.ldst_idx.stride.sz
RM.ldst_idx.sat
RM.ldst_idx.sat.N
RM.ldst_idx.sat.dz
RM.ldst_idx.sat.sz
RM.ldst_idx.prrc1
RM.ldst_idx.prrc1.inv
RM.ldst_idx.prrc1.CR
RM.ldst_idx.prrc0
RM.ldst_idx.prrc0.inv
RM.ldst_idx.prrc0.zz
RM.ldst_idx.prrc0.RC1
RM.ldst_idx.prrc0.dz
RM.ldst_idx.prrc0.sz

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