[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #2)
> I wanted to start 911, but hey, I got carried by the world of disassembly,
> and started checking into extra stuff (no pun intended, I'm really speaking
> of EXTRA). I've augmented DynamicOperandGPR and DynamicOperandFPR with
> information on these.

ah brilliant because the next step to add the extra bits should be
straightforward.
>     RT
>         01010
>         [6, 7, 8, 9, 10]
>         EXTRA[0]

suggest putting EXTRA3, (see Etype) so EXTRA3[0] is RM.EXTRA3[0] bits 0-2

>     RA
>         00000
>         [11, 12, 13, 14, 15]
>         EXTRA[1]

RM.EXTRA3[1] is RM.EXTRA bits 3-5
>     RB
>         00001
>         [16, 17, 18, 19, 20]
>         EXTRA[2]

and this is RM.EXTRA3[2] which is RM.EXTRA bits 6-8

from there checking bit 0 of each tells you "scalar or vector".
then appending the extra bits should be easy enough to make the
right regnum.

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