[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #4 from Dmitry Selyutin <ghostmansd at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> suggest putting EXTRA3, (see Etype) so EXTRA3[0] is RM.EXTRA3[0] bits 0-2

Ah yeah awesome idea! I thought about putting it on a separate line, but your
suggestion is much better, it expresses the intent in a much cleaner way. I'll
do it now.

> from there checking bit 0 of each tells you "scalar or vector".
> then appending the extra bits should be easy enough to make the
> right regnum.

I really thought that "if self.vector: prepend_asterisk(name)" is really clear
and obvious. So yeah this is largely the reason why this was placed in operand
classes. :-)

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