[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #2 from Dmitry Selyutin <ghostmansd at gmail.com> ---
I wanted to start 911, but hey, I got carried by the world of disassembly, and
started checking into extra stuff (no pun intended, I'm really speaking of
EXTRA). I've augmented DynamicOperandGPR and DynamicOperandFPR with information
on these.

40 0a 40 05    sv.add
14 6a e2 7e
    spec
        sv.add RT,RA,RB (OE=0 Rc=0)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00001010
        [24:32] 01000000
        [32:40] 01111110
        [40:48] 11100010
        [48:56] 01101010
        [56:64] 00010100
    opcode
        0x7c000214
    mask
        0xfc0007ff
    RT
        01010
        [6, 7, 8, 9, 10]
        EXTRA[0]
    RA
        00000
        [11, 12, 13, 14, 15]
        EXTRA[1]
    RB
        00001
        [16, 17, 18, 19, 20]
        EXTRA[2]
    OE
        0
        [21]
    Rc
        0
        [31]
    mode
        normal: simple

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