[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #58 from Dmitry Selyutin <ghostmansd at gmail.com> ---
OK we have the first specifiers: vec2, vec3, vec4.

ff ff ff 07    sv.add./vec4 *r3,*r7,*r11
15 12 01 7c

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