[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #57 from Dmitry Selyutin <ghostmansd at gmail.com> ---
Refactored RM handling again, fixed multiple issues in both power_insn and
power_fields modules in scope of these works. Also now RM types inherit the
docstring, so we no longer need some table between RM classes and descriptions.
Below is an example of what we have for now. As usual, this resides in dis
branch; the work is experimental, but I checked pysvp64dis test and it still
works.

ff ff ff 07    sv.add. *r3,*r7,*r11
15 12 01 7c    
    spec
        sv.add. RT,RA,RB (OE=0 Rc=1)
    pcode
        RT <- (RA) + (RB)
    binary
        [0:8]   00000111
        [8:16]  11111111
        [16:24] 11111111
        [24:32] 11111111
        [32:40] 01111100
        [40:48] 00000001
        [48:56] 00010010
        [56:64] 00010101
    opcodes
        011111---------------01000010101
    RT (vector)
        0000011
        38, 39, 40, 41, 42, 19, 20
        extra3[0]
    RA (vector)
        0000111
        43, 44, 45, 46, 47, 22, 23
        extra3[1]
    RB (vector)
        0001011
        48, 49, 50, 51, 52, 25, 26
        extra3[2]
    OE
        0
        53
    Rc
        1
        63
RM
        normal: Rc=1: pred-result CR sel
        RM
            111111111111111111111111
            6, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25, 26, 27, 28, 29, 30, 31
        RM.mmode
            1
            6
        RM.mask
            111
            8, 10, 11
        RM.elwidth
            11
            12, 13
        RM.ewsrc
            11
            14, 15
        RM.subvl
            11
            16, 17
        RM.mode
            11111
            27, 28, 29, 30, 31
        RM.smask
            111
            24, 25, 26
        RM.extra
            111111111
            18, 19, 20, 21, 22, 23, 24, 25, 26
        RM.extra2
            111111111
            18, 19, 20, 21, 22, 23, 24, 25, 26
        RM.extra2.idx0
            11
            18, 19
        RM.extra2.idx1
            11
            20, 21
        RM.extra2.idx2
            11
            22, 23
        RM.extra2.idx3
            11
            24, 25
        RM.extra3
            111111111
            18, 19, 20, 21, 22, 23, 24, 25, 26
        RM.extra3.idx0
            111
            18, 19, 20
        RM.extra3.idx1
            111
            21, 22, 23
        RM.extra3.idx2
            111
            24, 25, 26
        RM.inv
            1
            10
        RM.CR
            11
            11, 12

-- 
You are receiving this mail because:
You are on the CC list for the bug.