[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #59 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #58)
> OK we have the first specifiers: vec2, vec3, vec4.
> 
> ff ff ff 07    sv.add./vec4 *r3,*r7,*r11
> 15 12 01 7c

added unit test test_10_vec

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=2fbdc7f20190afaa98a504708ae2114107f765e4

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