[Libre-soc-bugs] [Bug 864] implement parallel prefix reduction in simulator

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=864

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
added sv/trans/svp64.py support (non-subvector mode)

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=8ea6301cecb6f6a61b140cf1b10f23bdbb161961

added to SVP64RMModeDecode

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=806cd6e0f2239ee12aef3d2ee96cf2a14a54d13b

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