[Libre-soc-bugs] [Bug 864] implement parallel prefix reduction in simulator

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=864

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 80c5c65b2e24c0c813e18e118f79bc120ffbfb20 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Tue Sep 6 15:28:05 2022 +0100

    REMAP parallel-reduce:
    https://bugs.libre-soc.org/show_bug.cgi?id=864
    * add 0b0111 csv entry for svshape
    * stop sv/trans/svp64.py raising exception for SVrm=0b0111
    * add beginnings of svshape SVrm=0b0111 to simplev.mdwn
    * add first unit test

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=80c5c65b2e24c0c813e18e118f79bc120ffbfb20

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