[Libre-soc-bugs] [Bug 864] implement parallel prefix reduction in simulator

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=864

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit e88b945123f2c3f047748a44fdf446775517076a (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Tue Sep 6 15:50:35 2022 +0100

    add first functional confirmed unit test for parallel reduce REMAP
    https://bugs.libre-soc.org/show_bug.cgi?id=864
    using remap_preduce_yield directly, confirmed operational through ISACaller
    added through decoder/isa/svshape.py which is responsible
    in SVSHAPE.getiterator() for returning the appropriate yield-iterator

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=e88b945123f2c3f047748a44fdf446775517076a

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