[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #61 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #60)

> This produces RM 0b000010000010010000000000. However, the original code did
> this:
> 
> -            sv_mode = ((bc_svstep << SVP64MODE.MOD2_MSB) |
> -                       (bc_vlset << SVP64MODE.MOD2_LSB) |
> -                       (bc_snz << SVP64MODE.BC_SNZ))
> -            srcwid = (bc_vsb << 1) | bc_lru
> -            destwid = (bc_lru << 1) | bc_all
> 
> This doesn't look like the correct thing (or at least it doesn't matches the
> table, where LRu goes to bit 22 and ALL goes to bit 4; same with VSb and
> (again??) LRu. For now it looks that the original code was incorrect, but
> I'd like to have a confirmation on this guess.

chances are high that if it worked before and you made changes that did
not match what worked because of assumptions "it must be wrong therefore
it must be changed", that the assumptions are wrong.

that, or the only thing ever tested was the "all" mode (which it is,
in the unit test).


consts.py.

19-23 = 0-4 in SVP64MODEb.

SVP64MODE.MOD2_MSB=0 ==> 19 => CTR mode (formerly bc_svstep)
SVP64MODE.MOD2_LSB=1 ==> 20 => VLset (correct)
SVP64MODE.BC_SNZ=3   ==> 22 => LRu not SNZ  - never tested but hey
srcwid =>               6/7 => CTi/VSB not VSB/LRu - never tested
destwid ->              4/5 => LRU/ALL not SNZ/all - probably wrong way.

so yes it's just "mostly borked" rather than "totally borked".

look in power_svp64_rm.py you will probably find i have the bit-order
on these the wrong way round:

            # Counter-Test Mode.
            with m.If(mode[SVP64MODE.BC_CTRTEST]):
                with m.If(self.rm_in.ewsrc[0]):
                    comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST_INV)
                with m.Else():
                    comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST)

            # BC Mode ALL or ANY (Great-Big-AND-gate or Great-Big-OR-gate)
            comb += self.bc_gate.eq(self.rm_in.elwidth[0])
            # Link-Register Update
            comb += self.bc_lru.eq(self.rm_in.elwidth[1])
            comb += self.bc_vsb.eq(self.rm_in.ewsrc[1])

swap these to:

            # Counter-Test Mode.
            with m.If(mode[SVP64MODE.BC_CTRTEST]):
                with m.If(self.rm_in.ewsrc[1]):
                    comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST_INV)
                with m.Else():
                    comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST)

            # BC Mode ALL or ANY (Great-Big-AND-gate or Great-Big-OR-gate)
            comb += self.bc_gate.eq(self.rm_in.elwidth[1])
            # Link-Register Update
            comb += self.bc_lru.eq(self.rm_in.elwidth[0])
            comb += self.bc_vsb.eq(self.rm_in.ewsrc[0])

and you'll likely find it "works"

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