[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #62 from Dmitry Selyutin <ghostmansd at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #61)
> the assumptions are wrong.

This is not some "assumption". I see mismatches between the tables and the
code. You look at the code and make an "assumption" this is correct, but it
contradicts the spec.
https://libre-soc.org/openpower/sv/branches/

> that, or the only thing ever tested was the "all" mode (which it is,
> in the unit test).

And the position of it is wrong.

> destwid ->              4/5 => LRU/ALL not SNZ/all - probably wrong way.

ALL/SNZ in spec. In this exact order.

> so yes it's just "mostly borked" rather than "totally borked".

Mostly or totally depends on the spec. I consider the spec, since it was
changed recently along with power_insn.

> look in power_svp64_rm.py you will probably find i have the bit-order
> on these the wrong way round:

Again: the "wrong" way depends on which resource we consider first, the code or
the spec. If I recall correctly, spec edits were recent.

> and you'll likely find it "works"

Either it works (without quotes), or the spec is "correct". And the point of
that long post was to find out which of these should be considered first.

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