[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #70 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
+                elif encmode == 'ctr':
+                    svp64_rm.branch.CTR = 1
+                    svp64_rm.branch.VLS = 0   <--- needs taking out
+                    svp64_rm.branch.ctr.CTi = 1
+                elif encmode == 'cti':
+                    svp64_rm.branch.CTR = 1
+                    svp64_rm.branch.ctr.CTi = 1

CTR and VLset mode can be combined!

-                elif encmode == 'snz':  # sz (only) already set above
-                    src_zero = 1
-                    bc_snz = 1
+                elif encmode == 'snz':
+                    svp64_rm.branch.SNZ = 1

notice how src_zero=1 was removed? that's a bug.  src_zero=1
*must* be enabled if snz is requested.  this makes disasm
"/sz/snz" redundant: it's either "/sz" or "/snz" or neither.

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