[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Sep 20 09:16:08 BST 2022


https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #71 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
this is the pseudocode for sv.bc:

  lr_ok <- LK
  svlr_ok <- SVRMmode.SL
  if ctr_ok & cond_ok then
    if SVRMmode.LRu then lr_ok <- ¬lr_ok
    if SVRMmode.SLu then svlr_ok <- ¬svlr_ok
  if lr_ok   then LR   <-iea CIA + 4
  if svlr_ok then SVLR <- SVSTATE

that means *four* permutations *each* for:

* LK=0/1 and LRu=0/1
* SL=0/1 and SLu=0/1

/lru we can do nothing about, it combines with the mnemonic name,
"bc" or "bcl".  in theory it would be possible to chuck in the
letter "u" on that. "sv.bcu", "sv.bclu".

svlr could be done similarly but keeping it to 3 letters max.
"/sl" and "/slu" and "/sll" or
"/s"      "/slu      "/sl" or
"/sl"     "/slu"     "sli" where this last is for SL=0,SLu=1

/s is fine because it will not be used elsewhere.

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