[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #21 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
$ echp 'sv.add *97,*23,*63' > svadd.tst.s
$ powerpc64le-linux-gnu-as svadd.tst.s 
$ powerpc64le-linux-gnu-objdump -D ./a.out 
0000000000000000 <.text>:
   0:   e0 2f 40 05     .long 0x5402fe0
   4:   14 7a 05 7f     add     r24,r5,r15
$ echo -n -e '\xe0\x2f\x40\x05\x14\x7a\x05\x7f' | pysvp64dis -v
e0 2f 40 05    sv.add *r97,*r23,*r63
14 7a 05 7f
    spec
        sv.add RT,RA,RB (OE=0 Rc=0)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00101111
        [24:32] 11100000
        [32:40] 01111111
        [40:48] 00000101
        [48:56] 01111010
        [56:64] 00010100
    opcode
        0x7c000214
    mask
        0xfc0007ff
    RT
        1100001                    <- correct
        38, 39, 40, 41, 42, 19, 20 <- good
        extra3[0]
    RA
        0010111                    <- correct
        43, 44, 45, 46, 47, 22, 23 <- good
        extra3[1]
    RB
        0111111                    <- correct
        48, 49, 50, 51, 52, 25, 26 <- good
        extra3[2]
    OE
        0
        53
    Rc
        0
        63
    mode
        normal: simple

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