[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
confirmed vector EXTRA2 works.  repro:

$ echo "sv.lwzu *62,16(*48)" >> lwzu.tst.s
$ powerpc64le-linux-gnu-as lwzu.tst.s
$ powerpc64le-linux-gnu-objdump -D ./a.out
0000000000000000 <.text>:
   0:   00 3a 40 05     .long 0x5403a00
   4:   10 00 ec 85     lwzu    r15,16(r12)
$ echo -n -e '\x00\x3a\x40\x05\x10\x00\xec\x85' | pysvp64dis -v
00 3a 40 05    sv.lwzu *r62,16,*r48
10 00 ec 85
    spec
        sv.lwzu RT,D(RA)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00111010
        [24:32] 00000000
        [32:40] 10000101
        [40:48] 11101100
        [48:56] 00000000
        [56:64] 00010000
    opcode
        0x84000000
    mask
        0xfc000000
    RT
        0111110                     <- 62 (correct)
        38, 39, 40, 41, 42, 19, {0} <- good
        extra2[0]
    D
        0000000000010000
        48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63
    RA
        0110000                     <- 48 (correct)
        43, 44, 45, 46, 47, 23, {0} <- good
        extra2[2]
    mode
        ld/st imm: simple

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