[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #15 from Dmitry Selyutin <ghostmansd at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #13)
> >     BI
> >         01001
> >         43, 44, 45, 46, 47
> >     target_addr
> >         00000000000010{00}
> >         48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61
> >         target_addr = EXTS(BD || 0b00))
> 
> nice. BD seems missing entirely but hey

Not quite entirely, cf. last line. :-) Also the range corresponds to BD and
formula explains this mystic {00}.

> this i assume is numbering based on 64-bit MSB0. it must be.
> if it's scalar it should be
> if that was vector it's correct.
> if it is scalar it should be {0}011110 [18,38,39....42]

Yeah this needs tuning then. Stay tuned. :-)

> this one is missing the 7-bit extension. no GPR/FPR/CR
> operands should miss EXTRA extension

This is caused by ambiguous wording "If EXTRA3 is zero, maps to "scalar
identity" (scalar Power ISA field naming)." (same for EXTRA2). So I printed
these as they were in SVP64-less world. But I can add these bits, not a big
deal.

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