[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #15)

> This is caused by ambiguous wording "If EXTRA3 is zero, maps to "scalar
> identity" (scalar Power ISA field naming)." (same for EXTRA2). So I printed
> these as they were in SVP64-less world. But I can add these bits, not a big
> deal.

ahh interesting.  technically-speaking, that's actually true.
so yes, that would work out fine.  had me confused for a minute.

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