[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #10)
> I've played a bit with the representation, here's what we have now:
> 
> 00 00 40 05    sv.bc 2,9,

wark-wark :)

> 08 00 49 40
>     spec
>         sv.bc BO,BI,target_addr (AA=0 LK=0)

niiice

>     BI
>         01001
>         43, 44, 45, 46, 47
>     target_addr
>         00000000000010{00}
>         48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61
>         target_addr = EXTS(BD || 0b00))

nice. BD seems missing entirely but hey

> 40 18 40 05    sv.add r127,r31,r65
> 14 0a ff 7f
>     spec
>         sv.add RT,RA,RB (OE=0 Rc=0)
>     RT
>         01111111
>         38, 39, 40, 41, 42, 18, 19, 20
>         extra3[0]

this i assume is numbering based on 64-bit MSB0. it must be.
* 38-42 minus 32 (to get them down to 32-bit MSB0) is 6-10
  ah ha! that matches with RT in a 32-bit instruction, so yes.

it also looks like it's vector numbering rather than scalar
numbering because 18,19,20 are at the end (in LSB positions)

if it's scalar it should be

    [19,20, 38, 39, 40, 41, 42] # or maybe 20,19,38..42


>     RA
>         11111
>         43, 44, 45, 46, 47
>         extra3[1]

this one is missing the 7-bit extension. no GPR/FPR/CR
operands should miss EXTRA extension


> 14 02 ef 7f    add r31,r15,r0
>     spec
>         add RT,RA,RB (OE=0 Rc=0)
>     RT
>         11111
>         6, 7, 8, 9, 10

yeah there we go.  6-10 (so 38-42 minus 32 was also 6-10)

> 00 15 40 05    sv.lwzu r30,16,r15
> 10 00 cf 87
>     spec
>         sv.lwzu RT,D(RA)
>     RT
>         011110{0}
>         38, 39, 40, 41, 42, 18
>         extra2[0]

if that was vector it's correct.

if it is scalar it should be {0}011110 [18,38,39....42]

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