[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #49 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

======================================================================
FAIL: test_7_batch (__main__.SVSTATETestCase) [58:bc]
these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25
----------------------------------------------------------------------
Traceback (most recent call last):
  File "openpower/sv/trans/test_pysvp64dis.py", line 27, in _do_tst
    "'%s' expected '%s'" % (line, expected[i]))
AssertionError: 'bc 16,0,-0xb4' != 'bc 16,0,0xff4c'
- bc 16,0,-0xb4
?         -  ^
+ bc 16,0,0xff4c
?           ^^ +
 : instruction does not match 'bc 16,0,0xff4c' expected 'bc 16,0,-0xb4'

58 means instruction 58 in the list tested.

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=6b844da793861c21b8221db4c17370502b740601

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