[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #5)
> OK, I started playing around SVP64 EXTRA2/EXTRA3 concepts. Here's what we
> have for now.
> Note the updated ranges for operands, the disassembly itself (first lines),
> and extra modes printed.
> 
> Yes I remember about target_addr. I just don't have time to do everything at
> once.
> 
> 00 00 40 05    sv.bc 2,9,0x8
> 08 00 49 40
>     spec
>         sv.bc BO,BI,BD (AA=0 LK=0)
>     binary
>         [0:8]   00000101
>         [8:16]  01000000
>         [16:24] 00000000
>         [24:32] 00000000
>         [32:40] 01000000
>         [40:48] 01001001
>         [48:56] 00000000
>         [56:64] 00001000
>     opcode
>         0x40000000
>     mask
>         0xfc000003
>     BO
>         00010
>         (38, 39, 40, 41, 42)
>     BI
>         01001
>         (43, 44, 45, 46, 47)
>     BD
>         00000000000010
>         (48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61)
>         target_addr = EXTS(BD || 0b00))
>     AA
>         0
>         (62,)
>     LK
>         0
>         (63,)
>     mode
>         branch
> 
> 40 18 40 05    sv.add r127,r31,r65
> 14 0a ff 7f
>     RB
>         01000001
>         (48, 49, 50, 51, 52, 24, 25, 26)
>         extra3[2]

ah! yeah, that looks right.  vector would
be:

    [48,49,50,51,52,24,25] # (or maybe 25,24)

scalar would be:

    [24,25,48,49,50,51,52,24,25] # (or maybe 25,24)


> 00 00 40 05    sv.lwzu r3,16,r1
> 10 00 61 84
>     spec
>         sv.lwzu RT,D(RA)

>     RA
>         00001
>         (43, 44, 45, 46, 47)
>         extra2[2]

and as this is EXTRA2, it would be best as:

     RA
         {0}000001
         [25,43,44,45,46,47] # or maybe 24

where vector would be:

         0000001{0}
         [43,44,45,46,47,25] # or maybe 24

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