[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #36 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
all good

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=b49d42520dbba44d6fc5421b57ea1202ed47252d

echo "sv.isel 10,20,30,*483" | pysvp64asm > svisel.tst.s 
echo -n -e '\xc0\x00\x40\x05\xde\xf7\x54\x7d' | pysvp64dis -v

c0 00 40 05    sv.isel r10,r20,r30,*483
de f7 54 7d    

    BC (vector)
        111100011
        53, 54, 55, 25, {0}, {0}, {0}, 56, 57
        extra2[3]




echo "sv.isel 10,20,30,63" | pysvp64asm > svisel.tst.s 
echo -n -e '\x40\x00\x40\x05\xde\xf7\x54\x7d' | pysvp64dis -v

40 00 40 05    sv.isel r10,r20,r30,63
de f7 54 7d    

    BC (scalar)
        000111111
        {0}, {0}, {0}, 25, 53, 54, 55, 56, 57
        extra2[3]

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