[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #30 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #29)
> From now on, we support pcode in extended mode, too.

nice idea for some ops - setvl and svshape on the other hand
are massive.  suggest it being an option.

> 00 38 40 05    sv.add *r3,r2,r1
> 14 0a 02 7c
>     spec
>         sv.add RT,RA,RB (OE=0 Rc=0)
>     pcode
>         RT <- (RA) + (RB)

>     RT (vector)
>     RA (scalar)

wha-hey!

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