[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #29 from Dmitry Selyutin <ghostmansd at gmail.com> ---
>From now on, we support pcode in extended mode, too.

00 38 40 05    sv.add *r3,r2,r1
14 0a 02 7c
    spec
        sv.add RT,RA,RB (OE=0 Rc=0)
    pcode
        RT <- (RA) + (RB)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00111000
        [24:32] 00000000
        [32:40] 01111100
        [40:48] 00000010
        [48:56] 00001010
        [56:64] 00010100
    opcode
        0x7c000214
    mask
        0x7c000615
    RT (vector)
        0000011
        38, 39, 40, 41, 42, 19, 20
        extra3[0]
    RA (scalar)
        00010
        43, 44, 45, 46, 47
        extra3[1]
    RB (scalar)
        00001
        48, 49, 50, 51, 52
        extra3[2]
    OE
        0
        53
    Rc
        0
        63
    mode
        normal: simple

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