[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #27 from Dmitry Selyutin <ghostmansd at gmail.com> ---
Refactored D operand so that it shows the verbose information in a more obvious
and explicit form.

47 00 90 59    fmvis f12,97
    spec
        fmvis FRS,D
    binary
        [0:8]   01011001
        [8:16]  10010000
        [16:24] 00000000
        [24:32] 01000111
    opcode
        0x58000006
    mask
        0x5800003e
    FRS
        01100
        6, 7, 8, 9, 10
    D
        d0 = D[0:9]
            0000000001
            16, 17, 18, 19, 20, 21, 22, 23, 24, 25
        d1 = D[10:15]
            10000
            11, 12, 13, 14, 15
        d2 = D[16]
            1
            31

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