[Libre-soc-bugs] [Bug 919] pysvp64dis: disassemble word instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=919

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #1)

> 2. I added support for LK and AA matching whenever one tries to find the
> instruction name in the database. Rc matching follows the same pattern.

briiilliant.  this is done manually for now, in PowerDecoder2 DecodeOE
(blegh)


            with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
                        MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
                        MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
                        MicrOp.OP_LOAD, MicrOp.OP_STORE,
                        MicrOp.OP_RLCL, MicrOp.OP_RLCR,
                        MicrOp.OP_SETVL, MicrOp.OP_SVSHAPE,
                        MicrOp.OP_SVINDEX, MicrOp.OP_SVREMAP,
                        MicrOp.OP_SVSTEP,
                        MicrOp.OP_EXTSWSLI, MicrOp.OP_GREV, MicrOp.OP_TERNLOG):
                pass

            # all other ops decode OE field
            with m.Default():

                    with m.Case(RC.RC):
                        comb += self.oe_out.data.eq(self.dec.OE)
                        comb += self.oe_out.ok.eq(1)

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