[Libre-soc-bugs] [Bug 919] pysvp64dis: disassemble word instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=919

--- Comment #2 from Dmitry Selyutin <ghostmansd at gmail.com> ---
We don't handle registers other than GPR and FPR yet, and don't (won't?) handle
aliases, but, other than that, I'd say we're close to completing. Do we need
support for pretty-printable CR_BIT/CR_REG? If so, how would it look in
assembly? IIRC binutils treat these like `bdzf    4*cr2+gt,0x14`. If so, that'd
be tricky a little bit, since we handle operand-per-operand, separated by
comma; but, considering real operands, there are three of them, not two (like
if we count commas).

-- 
You are receiving this mail because:
You are on the CC list for the bug.