[Libre-soc-bugs] [Bug 919] pysvp64dis: disassemble word instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=919

--- Comment #1 from Dmitry Selyutin <ghostmansd at gmail.com> ---
I've updated the disassembly with the following:
1. pysvp64dis prints the instructions themselves, too. This allows to analyze
the binary data simultaneously. Unknown instructions are printed as .long;
SVP64 instructions are printed in parts, with the first part dedicated to the
instruction and second empty (binutils way).
2. I added support for LK and AA matching whenever one tries to find the
instruction name in the database. Rc matching follows the same pattern.
3. The "database" classes hierarchy is changed, so the name matching applies to
SV-enabled instructions, too.
4. Various fixes, e.g. now we don't panic when there's a simple word
instruction followed by SVP64 instruction.

Below is an example of the output.

14 6a e2 7e    add r23,r2,r13
40 0a 40 05    sv.add
14 6a e2 7e
08 00 49 40    bc 2,9,0x8
00 00 40 05    sv.bc
08 00 49 40
15 02 41 7c    add. r2,r1,r0
21 04 80 4e    bcctrl 20,0,0
2b 00 85 40    bcla 4,5,0x28

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