[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #54 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #52)
> FAIL: test_7_batch (__main__.SVSTATETestCase) [26:mtspr]
>  : instruction does not match 'mtspr 9,0' expected 'mtspr 288,0'

got it.
https://libre-soc.org/openpower/isa/sprset/

n <- spr[5:9] || spr[0:4]

sigh.

solvable by adding a definition to fields.txt for spr
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isatables/fields.text;h=95c76fb77fbcbe99c45c0a41d39a7cf50a0636c9;hb=e3ebeaafbc0fc1864f05746c49c1b6b98b3e12ad

 827     SPR (11:20)

wark-wark  replace with

 827     SPR (16:20,11:15)

and altering the pseudocode to just "n <- spr"

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