[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #10 from Dmitry Selyutin <ghostmansd at gmail.com> ---
I've played a bit with the representation, here's what we have now:

00 00 40 05    sv.bc 2,9,
08 00 49 40
    spec
        sv.bc BO,BI,target_addr (AA=0 LK=0)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00000000
        [24:32] 00000000
        [32:40] 01000000
        [40:48] 01001001
        [48:56] 00000000
        [56:64] 00001000
    opcode
        0x40000000
    mask
        0xfc000003
    BO
        00010
        38, 39, 40, 41, 42
    BI
        01001
        43, 44, 45, 46, 47
    target_addr
        00000000000010{00}
        48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61
        target_addr = EXTS(BD || 0b00))
    AA
        0
        62
    LK
        0
        63
    mode
        branch

40 18 40 05    sv.add r127,r31,r65
14 0a ff 7f
    spec
        sv.add RT,RA,RB (OE=0 Rc=0)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00011000
        [24:32] 01000000
        [32:40] 01111111
        [40:48] 11111111
        [48:56] 00001010
        [56:64] 00010100
    opcode
        0x7c000214
    mask
        0xfc0007ff
    RT
        01111111
        38, 39, 40, 41, 42, 18, 19, 20
        extra3[0]
    RA
        11111
        43, 44, 45, 46, 47
        extra3[1]
    RB
        01000001
        48, 49, 50, 51, 52, 24, 25, 26
        extra3[2]
    OE
        0
        53
    Rc
        0
        63
    mode
        normal: simple

14 02 ef 7f    add r31,r15,r0
    spec
        add RT,RA,RB (OE=0 Rc=0)
    binary
        [0:8]   01111111
        [8:16]  11101111
        [16:24] 00000010
        [24:32] 00010100
    opcode
        0x7c000214
    mask
        0xfc0007ff
    RT
        11111
        6, 7, 8, 9, 10
    RA
        01111
        11, 12, 13, 14, 15
    RB
        00000
        16, 17, 18, 19, 20
    OE
        0
        21
    Rc
        0
        31

00 15 40 05    sv.lwzu r30,16,r15
10 00 cf 87
    spec
        sv.lwzu RT,D(RA)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00010101
        [24:32] 00000000
        [32:40] 10000111
        [40:48] 11001111
        [48:56] 00000000
        [56:64] 00010000
    opcode
        0x84000000
    mask
        0xfc000000
    RT
        011110{0}
        38, 39, 40, 41, 42, 18
        extra2[0]
    D
        0000000000010000
        48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63
    RA
        001111{0}
        43, 44, 45, 46, 47, 22
        extra2[2]
    mode
        ld/st imm: simple

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