[Libre-soc-bugs] [Bug 920] pysvp64dis: disassemble SVP64 instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=920

--- Comment #2 from Dmitry Selyutin <ghostmansd at gmail.com> ---
Just started implementing the verbose mode for SVP64-augmented instructions.
Currently very similar to word instructions (in fact, most of the methods
operate on the suffix).

40 0a 40 05    sv.add
14 6a e2 7e
    spec
        sv.add RT,RA,RB (OE=0 Rc=0)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00001010
        [24:32] 01000000
        [32:40] 01111110
        [40:48] 11100010
        [48:56] 01101010
        [56:64] 00010100
    opcode
        0x7c000214
    mask
        0xfc0007ff
    RT
        01010
        [6, 7, 8, 9, 10]
    RA
        00000
        [11, 12, 13, 14, 15]
    RB
        00001
        [16, 17, 18, 19, 20]
    OE
        0
        [21]
    Rc
        0
        [31]

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