[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #18 from Dmitry Selyutin <ghostmansd at gmail.com> ---
OK yet another take on these, never surrender! Note that I refactored the
representation and {0} appears for the fields instead, this looks much clearer
and explains what happens better (especially with extras).
00 00 40 05    sv.bc 2,9,0x8
08 00 49 40
    spec
        sv.bc BO,BI,target_addr (AA=0 LK=0)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00000000
        [24:32] 00000000
        [32:40] 01000000
        [40:48] 01001001
        [48:56] 00000000
        [56:64] 00001000
    opcode
        0x40000000
    mask
        0xfc000003
    BO
        00010
        38, 39, 40, 41, 42
    BI
        01001
        43, 44, 45, 46, 47
    target_addr
        0000000000001000
        48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, {0}, {0}
        target_addr = EXTS(BD || 0b00))
    AA
        0
        62
    LK
        0
        63
    mode
        branch

40 18 40 05    sv.add r127,r31,r65
14 0a ff 7f
    spec
        sv.add RT,RA,RB (OE=0 Rc=0)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00011000
        [24:32] 01000000
        [32:40] 01111111
        [40:48] 11111111
        [48:56] 00001010
        [56:64] 00010100
    opcode
        0x7c000214
    mask
        0xfc0007ff
    RT
        1111111
        19, 20, 38, 39, 40, 41, 42
        extra3[0]
    RA
        11111
        43, 44, 45, 46, 47
        extra3[1]
    RB
        1000001
        25, 26, 48, 49, 50, 51, 52
        extra3[2]
    OE
        0
        53
    Rc
        0
        63
    mode
        normal: simple

14 02 ef 7f    add r31,r15,r0
    spec
        add RT,RA,RB (OE=0 Rc=0)
    binary
        [0:8]   01111111
        [8:16]  11101111
        [16:24] 00000010
        [24:32] 00010100
    opcode
        0x7c000214
    mask
        0xfc0007ff
    RT
        11111
        6, 7, 8, 9, 10
    RA
        01111
        11, 12, 13, 14, 15
    RB
        00000
        16, 17, 18, 19, 20
    OE
        0
        21
    Rc
        0
        31

00 15 40 05    sv.lwzu r62,16,r63
10 00 df 87
    spec
        sv.lwzu RT,D(RA)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00010101
        [24:32] 00000000
        [32:40] 10000111
        [40:48] 11011111
        [48:56] 00000000
        [56:64] 00010000
    opcode
        0x84000000
    mask
        0xfc000000
    RT
        0111110
        19, {0}, 38, 39, 40, 41, 42
        extra2[0]
    D
        0000000000010000
        48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63
    RA
        0111111
        23, {0}, 43, 44, 45, 46, 47
        extra2[2]
    mode
        ld/st imm: simple

00 25 40 05    sv.lwzu *r0,16,r63
10 00 1f 84
    spec
        sv.lwzu RT,D(RA)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00100101
        [24:32] 00000000
        [32:40] 10000100
        [40:48] 00011111
        [48:56] 00000000
        [56:64] 00010000
    opcode
        0x84000000
    mask
        0xfc000000
    RT
        0000000
        38, 39, 40, 41, 42, 19, {0}
        extra2[0]
    D
        0000000000010000
        48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63
    RA
        0111111
        23, {0}, 43, 44, 45, 46, 47
        extra2[2]
    mode
        ld/st imm: simple

00 35 40 05    sv.lwzu *r2,16,r63
10 00 1f 84
    spec
        sv.lwzu RT,D(RA)
    binary
        [0:8]   00000101
        [8:16]  01000000
        [16:24] 00110101
        [24:32] 00000000
        [32:40] 10000100
        [40:48] 00011111
        [48:56] 00000000
        [56:64] 00010000
    opcode
        0x84000000
    mask
        0xfc000000
    RT
        0000010
        38, 39, 40, 41, 42, 19, {0}
        extra2[0]
    D
        0000000000010000
        48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63
    RA
        0111111
        23, {0}, 43, 44, 45, 46, 47
        extra2[2]
    mode
        ld/st imm: simple

There's one quirk still: `sv.lwzu *r2,16,r63` should have rather been `sv.lwzu
*r2,16(r63)`. I'll update it.

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