[Libre-soc-bugs] [Bug 890] Static Timing Analysis of eth_mac

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Sep 13 00:50:21 BST 2022


https://bugs.libre-soc.org/show_bug.cgi?id=890

--- Comment #30 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
(In reply to Jean-Paul Chaput from comment #29)
>   I didn't follow closely your rebuild efforts, but did you use the
>   system-wide flex or the 2.5.4 version supplied with Tas/Yagle sources?
>   I am not a hundred percent sure, but I seems to recall that using any
>   other version of flex produce what you are observing.

Tested in a fresh debian 10 chroot to make sure the tas-yagle 2.5.4 flex is
used. Removed 'flex' package from the "install-hdl-apt-reqs" script (installs
typical build/lang packages).

The output of running the inverter ./db.tcl has now changed:
LOADING FILE inv
 00min 00s
hitas user   : 00'00.0''
      system : 00'00.0''
-----------------------------------
DISASSEMBLING:
Check level II (nets)
Transistor netlist checking              00m00s  u:00m00.0  M:25288Kb
Extracting CMOS duals                    00m00s  u:00m00.0  M:25584Kb
Check level III (cones)
Extracting bleeders                      00m00s  u:00m00.0  M:25584Kb
Making gates                             00m00s  u:00m00.0  M:25584Kb
Latches detection                        00m00s  u:00m00.0  M:25584Kb
Making cells                             00m00s  u:00m00.0  M:25584Kb
External connector verification          00m00s  u:00m00.0  M:25584Kb
Checking the yagle figure                00m00s  u:00m00.0  M:25584Kb
------------------------------------------------------------
See file 'inv.rep' for more information
------------------------------------------------------------
 00min 00s
hitas user   : 00'00.0''
      system : 00'00.0''
-----------------------------------
CNS FILE inv.cns:
 00min 00s
hitas user   : 00'00.0''
      system : 00'00.0''
-----------------------------------
COMPUTING GATE DELAYS:
[Warning TRC-010]: The equivalent gate output load gives a negative capacitance
for signal y. 0 value is retained
[Error TRC-005]: Internal error #46 on net y.
** TOTAL ERRORS: 1
** TOTAL WARNINGS: 1


Output of inv.rep:
[WRN 01] VSS connector detected (0.000V) : 'gnd'
[WRN 01] VDD connector detected (1.620V) : 'vdd'

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