[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=917

--- Comment #67 from Dmitry Selyutin <ghostmansd at gmail.com> ---
BTW see how nice this BranchCTRVLSRM class is:

class BranchVLSRM(BranchBaseRM):
    """branch: VLSET mode"""
    VSb: BaseRM[7]
    VLI: BaseRM[21]

class BranchCTRRM(BranchBaseRM):
    """branch: CTR-test mode"""
    CTi: BaseRM[6]

class BranchCTRVLSRM(BranchVLSRM, BranchCTRRM):
    """branch: CTR-test+VLSET mode"""
    pass

I've omitted the specifiers section but these are inherited too. So we really
have CTR-test+VLSET, even in code. It inherits first from CTR-test RM, then
from VLS RM. To me this new hierarchy looks really cool, it literally matches
the spec.

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