[Libre-soc-bugs] [Bug 899] implement additional Transcendentals in simulator

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=899

--- Comment #28 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #27)
> I added svp64 tests for fptrans ops
> 
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=e3ebeaafbc0fc1864f05746c49c1b6b98b3e12ad

great! not too many i hope - running them all takes 15 mins already

> I also extended SimState to read all fprs/gprs/cr-fields so ExpectedState
> checks all of them, and outputs all of them to /tmp/expected.
>
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=6a3b3f88a962b72a7d833102888bbf72aa71d441

niice

> I also added the FRT, FRA, RB case to sv_analysis and checked all fptrans
> instructions in sv_analysis's output (I checked some instructions in each of
> the 3 different groups of fptrans instructions and assumed that all other
> instructions in each group (just changing the mnemonic and XO) won't make
> sv_analysis treat them differently).

no everything really is qualified by its register profile, how many src,
how many dest.  what the actual op is or its Form (X, D, MDS) is utterly
irrelevant.  XO likewise.  the only reason sone of the EXTRA allocations
are done through looking at the instruction name is, it's sometimes
easier and there are special cases (LDST-with-update)

> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=021bebb754c66c0b0ea0719a79a82f2e803cfe95

yyeah "TODO" in the CSV files, not so hot :)

it's relatively straightforward and obvious what needs to be done,
there.

> Now, the only stuff left to do is the binutils stuff, so I'm reassigning
> this to ghostmansd.

brilliant.

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