April 2020 Archives by thread
Starting: Wed Apr 1 00:01:56 BST 2020
Ending: Thu Apr 30 23:50:10 BST 2020
Messages: 561
- [libre-riscv-dev] PPC on Talos and Playstation 3
Luke Kenneth Casson Leighton
- [libre-riscv-dev] [Bug 272] functions needed in POWER simulator which match 3.0B spec
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] extremely busy crowdsupply update started
Cole Poirier
- [libre-riscv-dev] name change announcement on crowdsupply
Jacob Lifshay
- [libre-riscv-dev] submitted bugreport to upstream nmigen
Jacob Lifshay
- [libre-riscv-dev] test_decoder_gas.py still fails after update for unknown reason
Tobias Platen
- [libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 273] New: replace use of wget in soc with use of git submodule
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] POWER simulator
lkcl .
- [libre-riscv-dev] crowdsupply updates
Luke Kenneth Casson Leighton
- [libre-riscv-dev] [Bug 274] New: Investigate how BSV performs Formal Verification and what can be Applied to FPUs
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] April fools pull request for Rust
Jacob Lifshay
- [libre-riscv-dev] virtual coffee again
Luke Kenneth Casson Leighton
- [libre-riscv-dev] Public Inbox
Veera
- [libre-riscv-dev] [Bug 275] New: errata in V3.0B spec pseudo-code, page 88
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 185] Getting 502 Bad Gateway when accessing bugzilla from archive.org
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 185] Getting 502 Bad Gateway
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] finishing off the crowdsupply update
Jacob Lifshay
- [libre-riscv-dev] sorry state of ieee754fpu repo -- CI desperately needed
Jacob Lifshay
- [libre-riscv-dev] [Bug 276] New: SR NAND Latch needed in nmigrn
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 277] New: evaluate proposal of portions of nmutil for review and inclusion in nmigen
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] parser precedence, code review / checking needed
Luke Kenneth Casson Leighton
- [libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal 2019-10-031
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] 3.0B PDF spec parser and first auto-generator working well
Luke Kenneth Casson Leighton
- [libre-riscv-dev] [Bug 278] New: POWER v3.0B spec ambiguity on EXTS and missing EXTZ
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 279] New: inconsistency in 3.0B spec on definition of "equivalence" operator
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] Who Buys Talos Workstations?
Immanuel, Yehowshua U
- [libre-riscv-dev] SiFIve to go with PowerVR
Immanuel, Yehowshua U
- [libre-riscv-dev] POWER Spec parser nearly done
Luke Kenneth Casson Leighton
- [libre-riscv-dev] [Bug 280] New: POWER spec parser needs to support fall-through cases
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 281] New: put reverted code back (import of isa)
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] auto-generated simulator working??
Luke Kenneth Casson Leighton
- [libre-riscv-dev] [Bug 282] New: investigate partially-generating unit tests from spec
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] added CI to soc.git as well as attempting to fix all tests
Jacob Lifshay
- [libre-riscv-dev] [Bug 283] New: reversion of fields.text to fields.txt needed
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] Following the PowerISA
Immanuel, Yehowshua U
- [libre-riscv-dev] Open Power Registration
Immanuel, Yehowshua U
- [libre-riscv-dev] GStreamer and RUST
Immanuel, Yehowshua U
- [libre-riscv-dev] [OT] the microsoft hacker ("Baby Driver")
Luke Kenneth Casson Leighton
- [libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] Removing orphan pages from the wiki
Immanuel, Yehowshua U
- [libre-riscv-dev] nlnet 2019 standards update - video and 3d acceleration standards
Immanuel, Yehowshua U
- [libre-riscv-dev] [Bug 267] The efficiency of adder/subtractor
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] Broken build notification from debian salsa
Jacob Lifshay
- [libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 138] NLNet 2019 Coriolis2 Layout proposal 2019-10-029
bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] morphing 6600 code to use power decoder
Luke Kenneth Casson Leighton
- [libre-riscv-dev] [Bug 182] Move to libre-soc.org
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] test
Alain D D Williams
- [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] more build failures
Jacob Lifshay
- [libre-riscv-dev] POWER virtual coffee 5 mins (now)
lkcl .
- [libre-riscv-dev] [Bug 158] NLNet 2019 Formal Correctness Proofs toplevel 2019-10-032
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bugzilla] Your account libre-riscv-dev at lists.libre-riscv.org is being impersonated
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] libre-soc status: simulator and hardware "first instruction" execution
Luke Kenneth Casson Leighton
- [libre-riscv-dev] Pitch Speech
Immanuel, Yehowshua U
- [libre-riscv-dev] purism sponsorship
Luke Kenneth Casson Leighton
- [libre-riscv-dev] fork of qt contingency
Luke Kenneth Casson Leighton
- [libre-riscv-dev] email support for gitlab-ci-archiver
Jacob Lifshay
- [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 284] New: TypeError Object is not an nMigen signal
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 285] New: bugzilla to be made available "offline"
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 286] New: DataPointer concept: long-immediate references
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] LLHD: Rust is used to drive research in Hardware Design Languages
Jacob Lifshay
- [libre-riscv-dev] [Bug 174] NLNet 2019 Formal Standards OpenPOWER proposal 2019-10-046
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] style / commit messages
Luke Kenneth Casson Leighton
- [libre-riscv-dev] [Bug 287] New: corrections to commit f17100d6c435aec47b17acb188272a7e9b3cf67d
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 288] New: intro post for powerpc-notebook.org and https://www.powerprogress.org/en/
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 289] New: LD/ST Function Unit address match "vector" optimisation
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 290] New: import error caused by soc.decoder.isa.all no longer being generated
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] Yosys cxxrtl
Yehowshua Immanuel
- [libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 291] New: HDL Workflow and Coriolis2 chroot automated setup scripts
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] memory interface diagram woes
Jacob Lifshay
- [libre-riscv-dev] scammers looking for access to NLNet Funds
Luke Kenneth Casson Leighton
- [libre-riscv-dev] [Bug 292] New: implement multi-way read/write 6600 signals
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 81] implement 6600-style "precise" out-of-order scoreboard
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 173] dynamic partitioned "shift"
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 172] partitioned signal add/sub/neg
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 171] partitioned comparison operators
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 189] Create partitioned right shift using the existing partitioned left shift
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 211] formal proof of PowerDecoder stage2 needed
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 162] Formally Verify the FSGNJ module
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 165] Formally verify the FPCMP (FEQ, FLE, FLT) module
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 163] Formally Verify the FPMAX module
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 196] Formal correctness proof needed for the IEEE754 FPU
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 293] New: evaluate an online circuit-editor (with simulator preferably)
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 294] New: usage statistics needed for POWER9 architecture
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] [Bug 295] New: pay attention to these insights
bugzilla-daemon at libre-soc.org
- [libre-riscv-dev] sun opensparc t2
Jacob Lifshay
Last message date:
Thu Apr 30 23:50:10 BST 2020
Archived on: Thu Apr 30 23:50:22 BST 2020
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