[libre-riscv-dev] memory interface diagram woes

[Luke Kenneth Casson Leighton]

illustration, jacob.

with 8 LDST FUs, each with 2 64-bit data ports, how will those 16
entries be inserted into MemoryQueue?
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/memory_pipe_experiment/memory_queue.py;hb=HEAD

as in, not so much "how" (because in "coding terms" it's a "simple"
matter of writing the code).

i mean "how many wires will be required in order to multiplex up to
16x simultaneous 64-bit chunks into the same (one) MemoryQueue"?

l.