[libre-riscv-dev] [Bug 272] functions needed in POWER simulator which match 3.0B spec

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=272

--- Comment #13 from Michael Nolan <mtnolan2640 at gmail.com> ---
I've got something in decoder/selectable_int.py. It uses Power's bit ordering
so it should be good for the compiler but something to be aware of if it's used
anywhere else.

I'm not sure what to do about left shift and right shift. Should SelectableInt
(0x10, bits=8) << 4 equal SelectableInt(0x100, bits=12) or SelectableInt(0x00,
bits=8)

It's also unsigned only, I'm not sure how much that matters right now

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