[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=269

--- Comment #38 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
done, michael.  d0_d1_d2 is "non-standard".  probably should be dropped,
on reflection.


commit 3a40cddd16f77259c9f15edaa5aecb12f1a1324d (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Mon Apr 6 12:15:28 2020 +0100

    add individual field-detection where field spec is "d0,d1,d2"



Form DX
    field d0 BitRange([(0, 16), (1, 17), (2, 18), (3, 19), (4, 20), (5, 21),
(6, 22), (7, 23), (8, 24), (9, 25)])
    field d1 BitRange([(0, 11), (1, 12), (2, 13), (3, 14), (4, 15)])
    field d2 BitRange([(0, 31)])
    field d0_d1_d2 BitRange([(0, 16), (1, 17), (2, 18), (3, 19), (4, 20), (5,
21), (6, 22), (7, 23), (8, 24), (9, 25), (10, 11), (11, 12), (12, 13), (13,
14), (14, 15), (15, 31)])
    field RT BitRange([(0, 6), (1, 7), (2, 8), (3, 9), (4, 10)])
    field XO BitRange([(0, 26), (1, 27), (2, 28), (3, 29), (4, 30)])

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