[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=276

--- Comment #8 from whitequark at whitequark.org ---
> brilliant.  at a suitable time in the future we'd need a (quick) indicator on how to express $sr in nmigen

assert width == len(set) and width == len(clr) and width == len(q)
m.submodules += Instance("$sr",
    p_WIDTH=width,
    p_SET_POLARITY=1,
    p_CLR_POLARITY=1,
    i_SET=set,
    i_CLR=clr,
    o_Q=q)

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