[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=257

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
AXI4 does not have cache coherency either and yet it is still achieved. it is
done by passing messages over the "control bus", using home-grown protocols in
every case that i have examined (including ariane and OpenPITON).

we do not need to be fully compliant with the wishbone spec internally.

it is perfectly fine to modify the code so that it has the required bus
bandwidth for internal use.

when external connections to other peoples' code is needed (peripherals) then
and only then will we need to comply with the spec.

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