[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=269

--- Comment #26 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #21)
> i'm not happy at the deviations from the spec that have had to be made!
> the rather terrible solution is to have EXTZ and EXTS set the SelectableInt
> bitlength to (say) 1,000,000 then use that to detect that when you get this:
> 
>    x + EXTS(d)
> 
> it means that in the addition, the rhs takes the bit-length of x.
> 
> okok we can't do 1,000,000 bits because in EXTS that would be a 1,000,000 bit
> signed integer.  maybe... 256 bits or something.
> 
> i will modify SelectableInt so it is:
> 
>     def __add__(self, rhs):
>           if rhs.bits == 256:
>                rhs = SelectableInt(rhs.value, self.bits)
> 
> that will "do" as a workaround.

See bug 278, comment 1 for a better workaround that doesn't require giant bit
counts.

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