[libre-riscv-dev] LLHD: Rust is used to drive research in Hardware Design Languages

[Jacob Lifshay]

On Tue, Apr 14, 2020, 16:21 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Wednesday, April 15, 2020, Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > Found this very interesting paper on LLHD, a new IR for HDLs, in this
> > week's This Week in Rust:
> >
> > https://arxiv.org/pdf/2004.03494
> >
> > The website is:
> > http://llhd.io/
>
>
> aw not another one! and did they add it to yosys? if not it is
> unfortunately just a toy.  yosys is the defacto standard gateway to FPGAs
> and ASIC synthesis


Created an issue for adding RTLIL support:
https://github.com/fabianschuiki/llhd/issues/116

Jacob