[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=257

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #26)

> another "easier" way may be to simply have *FOUR* 64-bit Wishbone
> interfaces:
> 
> * L1 left LO-64
> * L1 left HI-64
> * L1 right LO-64
> * L1 right HI-64
> 
> then we "jam" those down onto a single 64-bit Wishbone interface
> using a standard Wishbone Bus arbiter

i was going to say that those could all be 4 independent L1 caches,
however both left ones and both right ones have the exact same address,
so it would be a waste of power.

*however*... the 16-bit byte read/write-enable lines back at L0 can be
split into two then ORed together to produce a *single* "LO-64" and "HI-64"
L1 cache line read/write.

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