[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=269

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
michael i've started doing code-fragments, they're created with
decoder/pseudo/pywriter.py

you'll need to run "make gitupdate" in the top level of the soc
directory, that will pull in the git submodule for the wiki

can you take a look, see what the code "actually" would need to
look like?  i'd like to keep it really clean and simple.

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