[libre-riscv-dev] morphing 6600 code to use power decoder

[Luke Kenneth Casson Leighton]

https://libre-soc.org/3d_gpu/compunit_multi_rw.png

argh.  the addition of Carry (and other registers) means that the
"simple" 2-in, 1-out Computation Unit is not going to work.
additionally, there are actually 3-in 2-out operations such as the
int-mul-and-add, and FP operations will need to modify FPSCR as well.

the original 6600 CompUnits *specifically* waited until *both*
incoming operand Register Read Ports were free, choosing *one signal
pair* (Rd_Req and Go_Read) to synchronise that.

with the strong possibility of not *having* more than two read ports
per stratification of the Register File (HI-ODD32, LO-ODD32,
HI-EVEN32, LO-EVEN32) the original scheme is not going to work.

therefore where previously there was only one RD_REQ-GO_RD pair,
*multiple* (individual) RD_REQ-GO_RD pairs are needed.

this requires some additional logic.  where previously, the logic was
just simply: ISSUE, GO_RD, GO_WR, where only one of those can be
active at any one time, it now has to be:

* ISSUE
* send out multiple RD-REQs
* wait for *ALL* GO_RD responses to come in
* ONLY THEN send out WR-REQs
* wait for *ALL* GO_WR responses to come in
* reset back to the start.

complicated.

l.