[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=276

--- Comment #11 from whitequark at whitequark.org ---
> i presume that given that yosys already has $sr, only nmigen will need  augmenting to produce $sr?

There's no augmenting necessary. I gave you the code above (the
`Instance("$sr"...)` that causes nMigen to emit a Yosys `$sr` cell.

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