[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=276

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to whitequark from comment #13)
> (In reply to Luke Kenneth Casson Leighton from comment #12)
> > could you let me know what amount you'd be happy to receive as a donation
> > from NLNet, for including $sr in cxxrtl?
> 
> As it turns out, there's actually already support for `$dffsr` latch in
> cxxrtl, which is what you need but with an extra clock. So `$sr` support
> would be about ten lines of code I have to copy and paste from the `$dffsr`
> case.

*snort*.  funny.  well, you're spending time here, which is important as it
defines the scope, solves the problem, and, due to the critical importance
for the project, easily justifies giving you something.

-- 
You are receiving this mail because:
You are on the CC list for the bug.