[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=288

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #5)
> (In reply to Luke Kenneth Casson Leighton from comment #4)
> > > The first iteration of LibreSOC targets a single-core at 180nm. Subsequent
> > > generations target more cores at a smaller node size.
> > 
> > looks good.  i'd put "target multiple SMP cores" though.  "more cores"
> > could mean "NUMA" or "SIMT".  SIMT is almost impossible to program for
> > general-purpose, and NUMA is a royal pain, memory-wise.
> 
> Sounds good, though, it would be NUMA if we have multiple chips wired
> together using OmniXpress or similar.

true


> Also, we should be consistent spelling Libre-SOC with the hyphen like we
> agreed.

good catch.

Libre-SOC is a Libre Hardware-Software project that aims to deliver a physical 
POWER compliant SOC that comes complete with a CPU, GPU, VPU, and DDR
controller. All the software and hardware from the drivers down to the RTL and
VLSI cells are libre-licensed. Libre-SOC is also providing the necessary
drivers amongst which include Kazan (a Vulkan 3D driver) and the full
bootloader and on-board boot firmware source.

The intended market includes customers who desire acceleration in the embedded
space without relying on ARM or 3rd party proprietary drivers that have been
know to break in the past.

The first iteration of Libre-SOC targets a single-core at 180nm. Subsequent
generations target SMP cores at a smaller node size, for typical use in SBC
designs.

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